Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs

  • Authors:
  • Shivam Bhasin;Nidhal Selmane;Sylvain Guilley;Jean-Luc Danger

  • Affiliations:
  • Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141) - TCP Project, Departement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE;Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141) - TCP Project, Departement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE;Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141) - TCP Project, Departement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE;Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141) - TCP Project, Departement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE

  • Venue:
  • HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
  • Year:
  • 2009

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Abstract

Security evaluation of various AES implementation against practical power attacks has been reported in literature. However, to the authors' knowledge, very few of the fault attacks reported on AES have been practically realized. Since sbox is a crucial element in AES, in this article, we evaluate the security of some unprotected AES implementations differing in sbox construction, targeted for FPGA. Here the faults have been generated practically by underpowering the targeted circuit. Then we correlate our results with the underlying architecture, along a methodology already suggested in other articles, albeit theoretically. We also carry out an extensive characterization of the faults, in terms of temporal localization. On the basis of our results, we reach the conclusion that the two cheaper implementations in terms of silicon area are also the more vulnerable against DFA when implemented without counter-measures.