From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications
MICROW '12 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops
Journal of Systems and Software
Detecting positive voltage attacks on CMOS circuits
Proceedings of the First Workshop on Cryptography and Security in Computing Systems
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Security evaluation of various AES implementation against practical power attacks has been reported in literature. However, to the authors' knowledge, very few of the fault attacks reported on AES have been practically realized. Since sbox is a crucial element in AES, in this article, we evaluate the security of some unprotected AES implementations differing in sbox construction, targeted for FPGA. Here the faults have been generated practically by underpowering the targeted circuit. Then we correlate our results with the underlying architecture, along a methodology already suggested in other articles, albeit theoretically. We also carry out an extensive characterization of the faults, in terms of temporal localization. On the basis of our results, we reach the conclusion that the two cheaper implementations in terms of silicon area are also the more vulnerable against DFA when implemented without counter-measures.