Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
PRESENT: An Ultra-Lightweight Block Cipher
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
SCARE of an Unknown Hardware Feistel Implementation
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Silicon-level Solutions to Counteract Passive and Active Attacks
FDTC '08 Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Theoretical and Practical Aspects of Mutual Information Based Side Channel Analysis
ACNS '09 Proceedings of the 7th International Conference on Applied Cryptography and Network Security
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Side-channel analysis of six SHA-3 candidates
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
Mutual Information Analysis: a Comprehensive Study
Journal of Cryptology - Special Issue on Hardware and Security
Efficient Dual-Rail Implementations in FPGA Using Block RAMs
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
CT-RSA'12 Proceedings of the 12th conference on Topics in Cryptology
Hi-index | 0.00 |
Design of cryptographic applications need special care. For instance, physical attacks like Side-Channel Analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the "leakage" of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA) are often used for hardware implementations for low to medium volume productions or when flexibility is needed. They offer many possibilities for the computation, like small Look-Up Tables (LUT) and embedded block memories (BRAM). Certain countermeasures can be deployed, like dual-rail logic or masking, to resist SCA on FPGA. However to design an effective countermeasure, it is of prime importance for a designer to know the main leakage sources of the device. In this article, we analyze the leakage source of a Xilinx Virtex V FPGA by studying 3 different AES architectures. The analysis is based on real measurements by using specific leakage models of the sensitive variable, adapted to each architecture. Our results demonstrate that, BRAM which were considered to leak less traditionally, are found to be equally vulnerable if we change the attack target from address register to output latch. Hence by providing important clues about the leakage, this study allows the designers to enhance the robustness of their implementation in FPGA.