ICCOM'08 Proceedings of the 12th WSEAS international conference on Communications
FPGA implementation of bluetooth 2.0 transceiver
ICOSSE'06 Proceedings of the 5th WSEAS international conference on System science and simulation in engineering
FPGA implementation of a W-CDMA system based on IP functions
CONTROL'05 Proceedings of the 2005 WSEAS international conference on Dynamical systems and control
| Hi-index | 0.00 |
Prototyping of wireless radio is one of the major stages of the entire development process. It invariably has an interface to the Analog to digital converters (ADC) / Digital to Analog converters (DAC) and RF front end. This paper discusses in detail the design issues and solutions for baseband- RF front end interface, of a wireless radio. In these kinds of systems, the FPGA tends to be connected to the baseband DSP processor through the system bus. The FPGA is then used to implement additional baseband processing, hardware accelerators, ADC/DAC interfaces and RF control, to name a few. The DSP processor will need to communicate with these components through the system bus. Some of these components require high bandwidth and others requires low bandwidth from the system bus. There is a need for a design approach where that avoids slow interfaces, such as RF control interface, from hogging the system bus, which in turn will affect the overall performance of the entire system. This paper presents a System Bus-SPI bridge design approach to mitigate the interfacing issues in wireless system prototyping, especially when the supporting hardware, like RF module, is predefined. The proposed design enables the DSP Processor to access the System Bus concurrently while the SPI programming is in progress. Verilog hardware description language is used to design the System bus -SPI Bridge and Modelsim is used to verify the functionality of the design. The proposed design was implemented on an Altera STRATIX II FPGA.