Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Imagine: Media Processing with Streams
IEEE Micro
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy: Research Articles
International Journal of Circuit Theory and Applications - CNN Technology
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Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNNdesigns, giving the systema 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.