Analog Integrated Circuits and Signal Processing
Analysis and implementation of a minimum-supply body-biased CMOS differential amplifier cell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a high-speed sample-and-hold circuit using a substrate-biasing-effect attenuated T switch
Microelectronics Journal
Measuring the uniqueness and variety of analog circuit design features
Integration, the VLSI Journal
| Hi-index | 0.00 |
Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4-VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches.