Design and exploitation of a high-performance SIMD floating-point unit for Blue Gene/L

  • Authors:

  • S. Chatterjee;L. R. Bachega;P. Bergner;K. A. Dockser;J. A. Gunnels;M. Gupta;F. G. Gustavson;C. A. Lapkowski;G. K. Liu;M. Mendell;R. Nair;C. D. Wait;T. J. C. Ward;P. Wu

  • Affiliations:

  • IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana;IBM Systems and Technology Group, Rochester, Minnesota;Qualcomm CDMA Technologies, Cary, North Carolina;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Software Group, Toronto Laboratory, Markham, Ontario, Canada;IBM Software Group, Toronto Laboratory, Markham, Ontario, Canada;IBM Software Group, Toronto Laboratory, Markham, Ontario, Canada;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Engineering and Technology Services, Rochester, Minnesota;IBM United Kingdom Limited, Winchester, England;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2005

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Abstract

We describe the design of a dual-issue single-instruction, multiple-data-like (SIMD-like) extension of the IBM PowerPC® 440 floating-point unit (FPU) core and the compiler and algorithmic techniques to exploit it. This extended FPU is targeted at both the IBM massively parallel Blue Gene®/L machine and the more pervasive embedded platforms. We discuss the hardware and software codesign that was essential in order to fully realize the performance benefits of the FPU when constrained by the memory bandwidth limitations and high penalties for misaligned data access imposed by the memory hierarchy on a Blue Gene/L node. Using both hand-optimized and compiled code for key linear algebraic kernels, we validate the architectural design choices, evaluate the success of the compiler, and quantify the effectiveness of the novel algorithm design techniques. Our measurements show that the combination of algorithm, compiler, and hardware delivers a significant fraction of peak floating-point performance for compute-bound-kernels, such as matrix multiplication, and delivers a significant fraction of peak memory bandwidth for memorybound kernels, such as DAXPY, while remaining largely insensitive to data alignment.