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ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
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Power-aware scheduling has been of great interest for systems whose energy consumption needs to be minimized. In this paper, we improve a voltage-scaling-based power-aware scheduling algorithm to reduce the task's energy consumption at the cost of a slower execution rate. The improved algorithm allows multiple scaling voltage levels of individual tasks in a task precedence graph and attempts to maximize the amount of energy saved while still meeting a deadline constraint. Five bounded number of processor scheduling algorithms are used as the basis for this improved power-aware scheduling. Other sophisticated scheduling algorithms can be easily embedded in our improved power-aware scheduling algorithm to reduce the energy consumption. We use the simulation program AnyLogic™ to implement an easy-to-use drag-and-drop interface for building large-scale task graphs and running various simulations. The simulation results demonstrate that our proposed scheduling can reduce the energy consumption and achieve more energy savings than the static voltage scaling step alone. In addition, our simulation tool also provides an efficient and effective means for building task graphs and viewing the scheduling results in the form of the Gantt chart. This simulation quickly facilitates the testing of the validity of a problem and its outcomes and greatly fosters learning.