Scalable network virtualization using FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
Proceedings of the ACM SIGCOMM 2010 conference
Customizing virtual networks with partial FPGA reconfiguration
Proceedings of the second ACM SIGCOMM workshop on Virtualized infrastructure systems and architectures
Network I/O fairness in virtual machines
Proceedings of the second ACM SIGCOMM workshop on Virtualized infrastructure systems and architectures
Customizing virtual networks with partial FPGA reconfiguration
ACM SIGCOMM Computer Communication Review
Efficient Gigabit Ethernet Switch Models for Large-Scale Simulation
PADS '10 Proceedings of the 2010 IEEE Workshop on Principles of Advanced and Distributed Simulation
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Verifying and enforcing network paths with icing
Proceedings of the Seventh COnference on emerging Networking EXperiments and Technologies
OFLOPS: an open framework for openflow switch evaluation
PAM'12 Proceedings of the 13th international conference on Passive and Active Measurement
Deep packet inspection tools and techniques in commodity platforms: Challenges and trends
Journal of Network and Computer Applications
Fast simulation of background traffic through fair queueing networks
Proceedings of the Winter Simulation Conference
From 1G to 10G: code reuse in action
Proceedings of the first edition workshop on High performance and programmable networking
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A packet generator and network traffic capture system has been implemented on the NetFPGA. The NetFPGA is an open networking platform accelerator that enables rapid development of hardware-accelerated packet processing applications. The packet generator application allows Internet packets to be transmitted at line rate on up to four Gigabit Ethernet ports simultaneously. Data transmitted is specified in a standard PCAP file, transferred to local memory on the NetFPGA card, then sent on the Gigabit links using a precise data rate, inter-packet delay, and number of iterations specified by the user. The hardware circuit also simultaneously operates as a packet capture system, allowing traffic to be captured from up to all four of the Gigabit Ethernet ports. Timestamps are recorded and traffic can be transferred back to the host and stored using the same PCAP format. The project has been implemented as a fully open-source project and serves as an exemplar project on how to build and distribute NetFPGA applications. All of the code (Verilog hardware, system software, verification scripts, makefiles, and support tools) can be freely downloaded from the NetFPGA.org website. Benchmarks comparing this hardware-accelerated application to the fastest available PC with a PCIe NIC shows that the FPGA-based hardware-accelerator far exceeds the performance possible using TCP-reply software.