Genetic programming II: automatic discovery of reusable programs
Genetic programming II: automatic discovery of reusable programs
Through the Labyrinth Evolution Finds a Way: A Silicon Ridge
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
Aspects of Digital Evolution: Evolvability and Architecture
PPSN V Proceedings of the 5th International Conference on Parallel Problem Solving from Nature
Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Variable Length Representation in Evolutionary Electronics
Evolutionary Computation
Modular Interdependency in Complex Dynamical Systems
Artificial Life
A multi-chromosome approach to standard and embedded cartesian genetic programming
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Acquiring evolvability through adaptive representations
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Evolving multiplier circuits by training set and training vector partitioning
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
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Many researchers have encountered the problem that the evolution of electronic circuits becomes exponentially more difficult when problems with an increasing number of outputs are tackled. Although this is an issue in both intrinsic and extrinsic evolution experiments, overcoming this problem is particularly challenging in the case of evolvable hardware, where logic and routing resources are constrained according to the given architecture. Consequently, the success of experiments also depends on how the inputs and outputs are interfaced to the evolvable hardware. Various approaches have been made to solve the multiple output problem: partitioning the task with respect to the input or output space, incremental evolution of sub-tasks or resource allocation. However, in most cases, the proposed methods can only be applied in the case of extrinsic evolution. In this paper, we have accordingly, focused on scaling problem of increasing numbers of outputs when logic circuits are intrinsically evolved. We raise a number of questions: how big is the performance drop when increasing the number of outputs? Can the resources of evolvable hardware be structured in a suitable way to overcome the complexity imposed by multiple outputs, without including knowledge about the problem domain? Can available resources in hardware still be efficiently used when pre-structured? In order to answer these questions, different structural implementations are investigated. We have looked at these issues in solving three problems: 4-bit parity, 2-bit adder and 2-bit multiplier.