A Hardware Architecture for SIFT Candidate Keypoints Detection

Authors:
Leonardo Chang;José Hernández-Palancar
Affiliations:
Advanced Technologies Application Center, Havana City, Cuba C.P. 12200;Advanced Technologies Application Center, Havana City, Cuba C.P. 12200
Venue:
CIARP '09 Proceedings of the 14th Iberoamerican Conference on Pattern Recognition: Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications
Year:
2009

Citing 6
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Abstract

This paper proposes a parallel hardware architecture for the scale-space extrema detection part of the SIFT (Scale Invariant Feature Transform) method. The implementation of this architecture on a FPGA (Field Programmable Gate Array) and its reliability tests are also presented. The obtained features are very similar to Lowe's. The system is able to detect scale-space extrema on a 320 ×240 image in 3 ms, what represents a speed up of 250x compared to a software version of the method.