A design process of switched Ethernet architectures according to real-time application constraints

  • Authors:
  • Jean-Philippe Georges;Nicolas Krommenacker;Thierry Divoux;Eric Rondeau

  • Affiliations:
  • Université Henri Poincaré, Nancy 1, Centre de Recherche en Automatique de Nancy (UMR 7039 CNRS-INPL-UHP), Faculté des Sciences BP 239, F-54506 Vanduvre lès Nancy Cedex, France;Université Henri Poincaré, Nancy 1, Centre de Recherche en Automatique de Nancy (UMR 7039 CNRS-INPL-UHP), Faculté des Sciences BP 239, F-54506 Vanduvre lès Nancy Cedex, France;Université Henri Poincaré, Nancy 1, Centre de Recherche en Automatique de Nancy (UMR 7039 CNRS-INPL-UHP), Faculté des Sciences BP 239, F-54506 Vanduvre lès Nancy Cedex, France;Université Henri Poincaré, Nancy 1, Centre de Recherche en Automatique de Nancy (UMR 7039 CNRS-INPL-UHP), Faculté des Sciences BP 239, F-54506 Vanduvre lès Nancy Cedex, France

  • Venue:
  • Engineering Applications of Artificial Intelligence
  • Year:
  • 2006

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Abstract

Ethernet networks are based on a medium access method which is not deterministic. The use of such networks in factory environments (which are strongly time constraints) can absolutely not guarantee that the applications requirements will be respected. This paper presents a method based on genetic algorithms to minimize end-to-end delays by providing a good distribution of the devices on the network switches. The objective function is defined by using the network calculus which is a deterministic theory and enables to determine bounded delays. In this paper, a case study is described: theoretical results are verified by a real experimentation and compared with results obtained with a network simulator.