Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers
International Journal of Circuit Theory and Applications
Measuring the uniqueness and variety of analog circuit design features
Integration, the VLSI Journal
Integration, the VLSI Journal
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This brief presents a single-capacitor active-feedback compensation (SCAFC) scheme for three-stage internal amplifiers driving small capacitive loads. The proposed SCAFC scheme can stabilize the three-stage amplifier by using only a single small-value compensation capacitor, thereby significantly reducing the amplifier implementation area. With the small-value compensation capacitor, the wide gain-bandwidth product (GBW) of the SCAFC amplifier can also be achieved under low-power conditions. Implemented in a standard 0.35-µm CMOS process, the proposed three-stage SCAFC amplifier achieves over 100-dB dc gain, 9.6-MHz GBW, and 6.1-V/µs average slew rate, by only dissipating 90 µW at 1.5 V and using a 1-pF compensation capacitor, when driving a 500-kΩ // 20-pF load. The proposed SCAFC amplifier experimentally improves both bandwidth-to-power and slew-rate-to-power efficiencies by more than 14 times and 9 times, respectively, as compared to a conventional three-stage nested-Miller-compensated amplifier.