A fast spline curve rendering accelerator architecture

  • Authors:
  • Yun-Nan Chang

  • Affiliations:
  • Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan

  • Venue:
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • Year:
  • 2009

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Abstract

Spline curve rendering is an essential operation in modern 2-D graphic applications. Different from the software acceleration approach by graphic processor units, this brief presents a very large scale integration hardware accelerator architecture for supporting fast curve rendering. Many existing accelerators employ a sequential forward-difference algorithm, where a step size is used in calculating the next sample on the curve. The problem of hardware-based curve rendering is that feedback loops are required to accumulate the difference, and these loops inhibit many traditional performance-enhancement strategies such as unfolding and pipelining. This brief proposes a different parallel design approach by transforming the difference equation set into parallel ones. Each equation has to be equipped with the same increased step size but accumulated starting from different initial values. Although more initial values must be precomputed, this computation can itself be sped up by using the accelerator. The proposed design can be applied not only to cubic spline curves but also to any curves defined by parameterized polynomial functions.