A new architecture of a two-stage lossless data compression and decompression algorithm

Authors:
Ming-Bo Lin;Yung-Yi Chang
Affiliations:
Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.C.;Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.C.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

Citing 7
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Abstract

In this paper, we propose a new architecture for the two-level lossless data compression and decompression algorithm proposed in [8] that combines the PDLZW algorithm and an approximated adaptive Huffman algorithm with dynamic-block exchange (AHDB). In the new architecture, we replace the CAM dictionary set used in the PDLZW algorithm with a CAM-tag-based dictionary set to reduce hardware cost and the CAM-based ordered list used in the AHDB algorithm with a memory inter-reference (MIR) stage realized by using two SRAMs. The resulting architecture is then implemented based on cell-based libraries with both 0.35-µm 2P4M and 0.18-µm 1P6M process technologies, respectively. With the same process technology, the prototyped chip demonstrates the new architecture not only has better performance, at least 33% improvement, but also occupies less area, only about 44%, and consumes less power, about 50%, in comparison with the architecture proposed in [8]. In addition, the maximum data rate can achieve 2 Gbps when realizing in 0.35 µm 2P4M process technology and 4 Gbps when realizing in 0.18-µm 1P6M process technology.