Knapsack problems: algorithms and computer implementations
Knapsack problems: algorithms and computer implementations
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Operating Systems: Program overlay techniques
Communications of the ACM
Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A post-compiler approach to scratchpad mapping of code
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Dynamic allocation for scratch-pad memory using compile-time decisions
ACM Transactions on Embedded Computing Systems (TECS)
Software-based instruction caching for embedded processors
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Paul Wilmott Introduces Quantitative Finance
Paul Wilmott Introduces Quantitative Finance
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Due to the need to reduce power, size, and the requirement for real time access of both data and code, large caches have fallen out of favour for many embedded processors. Replaced by small software managed scrachpads a number of designs have been presented for managing the dynamic movement of data and/or code to and from larger, less responsive memories. To date these approaches have been deemed unnecessary in the context of memory contention. However this trend is changing with the introduction of highly parallel components as co-processors in SOC designs. While the same arguments concerning caches continue to be made in this context it is also the contention for bus and memory bandwidth that is seeing numerous levels of memory placed closer and closer to the core(s). Unlike the scratchpads seen thus far in the embedded domain often these memories can be hundreds of kilobytes and thus are capable of holding large working sets and in some cases even complete applications. In this paper we present an alternative approach to managing on-chip memory. A simple set of directives is provided, allowing the programmer to describe 'overlays', themselves containing groupings of sub-routines, which are managed at runtime between on-chip and off-chip memories.