Dynamically reconfigurable regular expression matching architecture
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Automatically mapping applications to a self-reconfiguring platform
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic circuit specialisation for key-based encryption algorithms and DNA alignment
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Automating reconfiguration chain generation for SRL-Based run-time reconfiguration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
How to efficiently implement dynamic circuit specialization systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The Shift-Register-Lut (SRL) functionality is a powerful extension of Xilinx FPGA architectures and has been used successfully in many applications. If routing is kept fixed, these SRLs can also be used for run-time reconfiguration. So far, this technique has mainly been used to reconfigure specialized functions. In contrast, we propose a generic tool flow that uses SRLs for fast run-time reconfiguration of general data folding applications. We show that, in such an automatic toolflow, SRL reconfiguration is over two orders of magnitude faster than run-time reconfiguration using the ICAP. It thus makes run-time reconfiguration viable for applications with a more dynamic behaviour. Our generic tool flow is also very easy to use since the designer only has to annotate slowly varying signals in an RTL HDL description, while the tool flow takes care of all the rest.