Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A comparative analysis of schemes for correlated branch prediction
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The influence of branch prediction table interference on branch prediction scheme performance
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
The agree predictor: a mechanism for reducing negative branch history interference
Proceedings of the 24th annual international symposium on Computer architecture
Trading conflict and capacity aliasing in conditional branch predictors
Proceedings of the 24th annual international symposium on Computer architecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The YAGS branch prediction scheme
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Design tradeoffs for the Alpha EV8 conditional branch predictor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
The Alpha 21264 Microprocessor
IEEE Micro
Optimal 2-Bit Branch Predictors
IEEE Transactions on Computers
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
A novel meta predictor design for hybrid branch prediction
WSEAS Transactions on Computers
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High-performance computer systems have made use of super-pipelining, dynamic scheduling and multiissue superscalar processor technologies. In these systems, branch prediction accuracy has a significant impact on the performance because the penalty for misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. To have a better prediction accuracy, branch predictors utilized in high performance systems are a hybrid type. Hybrid branch prediction employs multiple branch predictors and selects one particular branch predictor per the program context of a given branch instruction instance for prediction. For choosing a particular branch predictor is a job of "meta-predictor". This paper considers type and size of saturating counter design specifically for the meta predictor. State transitions different from a usual saturating counter may choose a particular predictor for prediction better and result a higher prediction accuracy.