Production system for LSI chip anatomizing
Pattern Recognition Letters
An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques
IEEE Transactions on Pattern Analysis and Machine Intelligence
The P300: a system for automatic patterned wafer inspection
Machine Vision and Applications
Integrated Testing and Algorithms for Visual Inspection of Integrated Circuits
IEEE Transactions on Pattern Analysis and Machine Intelligence
Pattern Recognition Letters
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Advances in integrated circuits technology lead to a continuous reduction in the size of individual features and to an increase in the size of chips and wafers. Every day it becomes more difficult to carry out tests and controls of quality and it is necessary to devise new techniques for accurate analysis of features, chips, and wafers. One of these procedures, visual inspection, can be achieved automatically by using image analysis techniques, with a high degree of automation and a low labor cost. We present a method for segmenting and classifying integrated circuit images based on one of these techniques: mathematical morphology.