SC filter for RF sampling and downconversion with wideband image rejection
Analog Integrated Circuits and Signal Processing
CMOS blocks for on-chip RF test
Analog Integrated Circuits and Signal Processing
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Digital RF processing: toward low-cost reconfigurable radios
IEEE Communications Magazine
| Hi-index | 0.00 |
In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5-6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 µm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 2× subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.