Analysis of op-amp phase margin impact on SC ΣΔ modulator performance

Authors:
Andrea Pugliese;Francesco A. Amoroso;Gregorio Cappuccino;Giuseppe Cocorullo
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Via P. Bucci, 42C, 87036-Rende (CS), Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Via P. Bucci, 42C, 87036-Rende (CS), Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Via P. Bucci, 42C, 87036-Rende (CS), Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Via P. Bucci, 42C, 87036-Rende (CS), Italy
Venue:
Microelectronics Journal
Year:
2010

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Abstract

The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (@S@DM) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35@mm CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in @S@DM behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase.