Design procedure for two-stage CMOS transconductance operational amplifiers: a tutorial
Analog Integrated Circuits and Signal Processing
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
An Overview of Analog Feedback Part I: Basic Theory
Analog Integrated Circuits and Signal Processing
Layout preferences concerning matching in a fully differential ΔΣ modulator design
Analog Integrated Circuits and Signal Processing
A 1.8-V 91-dB DR second-order ΣΔ modulator in 0.18-μm CMOS technology
Analog Integrated Circuits and Signal Processing
Switched capacitor analog modulo integrator for application in open loop Sigma-Delta modulators
Analog Integrated Circuits and Signal Processing
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Analysis of op-amp phase margin impact on SC ΣΔ modulator performance
Microelectronics Journal
Split compensation for inverter-based two-stage amplifier
Microelectronics Journal
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A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach defines a systematic procedure to optimize the amplifier time response, allowing the required speed performances to be achieved without both power wasting and blind efforts for time-consuming trial-and-error design processes. To demonstrate the effectiveness of the methodology, a design example in a commercial 0.35 μm CMOS technology is presented. As shown by circuit and statistical simulations, the proposed strategy proves to be very useful to develop fast-settling operational amplifiers for typical discrete-time applications, such as switched-capacitor filters and ΣΔ analog-to-digital converters.