A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver

Authors:
Ling Zhang;Hyung Joon Kim;Vinay Nadig;Mohammed Ismail
Affiliations:
-;-;Analog VLSI Lab, Department of Electrical and Computer Engineering, The Ohio State University, Columbus 43210;Analog VLSI Lab, Department of Electrical and Computer Engineering, The Ohio State University, Columbus 43210
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2006

Citing 1
Cited 3

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Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers

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Analysis of op-amp phase margin impact on SC ΣΔ modulator performance

Microelectronics Journal
Analysis of the impact of high-order integrator dynamics on SC sigma-delta modulator performances

IEEE Transactions on Circuits and Systems Part I: Regular Papers

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Abstract

The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable ΣΔ modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this ΣΔ modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-μm CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58 dB for WLAN.