Analysis of the impact of high-order integrator dynamics on SC sigma-delta modulator performances

Authors:
Andrea Pugliese;Francesco Antonio Amoroso;Gregorio Cappuccino;Giuseppe Cocorullo
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Cosenza, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Cosenza, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Cosenza, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Cosenza, Italy
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

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Abstract

The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator (ΣΔM) performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 µm CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit ΣΔMs characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the ΣΔM characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective ΣΔM design flow.