Designing globally optimal delta–sigma modulator topologies via signomial programming
International Journal of Circuit Theory and Applications
International Journal of Circuit Theory and Applications - ECCTD 2007
Analog calibration of channel mismatches in time-interleaved ADCs
International Journal of Circuit Theory and Applications - ECCTD 2007
Linearity analysis in pipeline A-D converters
International Journal of Circuit Theory and Applications
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Analysis of the impact of high-order integrator dynamics on SC sigma-delta modulator performances
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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A new solution to implement efficient switched-capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35−µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.