Voice over IP performance monitoring
ACM SIGCOMM Computer Communication Review
IXP-1200 Programming
DiffServ over Network Processors: Implementation and Evaluation
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Voice Quality Evaluation of IP-Based Voice Stream Multiplexing Schemes
LCN '01 Proceedings of the 26th Annual IEEE Conference on Local Computer Networks
Robust header compression (ROHC) in next-generation network processors
IEEE/ACM Transactions on Networking (TON)
Performance Evaluation of MPLS and IP on an IXP1200 Network Processor
AINA '06 Proceedings of the 20th International Conference on Advanced Information Networking and Applications - Volume 02
Fundamentals of Queueing Theory
Fundamentals of Queueing Theory
A survey on wireless mesh networks
IEEE Communications Magazine
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This paper proposes a numerical analysis model to predict the processing delay of a hardware architecture for robust header compression and packet aggregation on wireless mesh networks. The analysis model is composed of a series of queue systems such as G/M/1, M [K]/M/1, M/M/1, and M/M/驴 that are one-to-one mapped into the constructed hardware components to characterize the concurrent operations and interactional relationship between encoding and decoding paths. Based on the co-simulation method which integrates NS-2 and SystemC, we show the analysis model properly approximates the processing delay of the hardware architecture. Additionally, the variation of processing delay occurring when a part of hardware components are differently configured is suitably characterized by the proposed model, and the overall mesh network behaviors is predicted by applying the numerical results into NS-2 simulations.