A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
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MIMO-OFDM wireless systems: basics, perspectives, and challenges
IEEE Wireless Communications
IEEE 802.11 wireless LAN implemented on software defined radio with hybrid programmable architecture
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New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications
IEEE Transactions on Consumer Electronics
IEEE Communications Magazine
The software radio architecture
IEEE Communications Magazine
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In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable lengths of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and implemented with Xilinx Virtex-4 FPGA. With the proposed architecture, the number of slices for the processor is 1784, the number of DSP48s (dedicated multiplier) is 48, and the size of memory is 90Kbits, which are reduced by 41.9%, 62.5% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the number of slices, the number of DSP48s and memory size are reduced by 26.2%, 25% and 26.8%, respectively.