Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer
SIAM Journal on Computing
Transformation rules for designing CNOT-based quantum circuits
Proceedings of the 39th annual Design Automation Conference
Quantum computation and quantum information
Quantum computation and quantum information
Improving Gate-Level Simulation of Quantum Circuits
Quantum Information Processing
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
Data structures and algorithms for simplifying reversible circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Checking equivalence of quantum circuits and states
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Implementation of Shor's algorithm on a linear nearest neighbour qubit array
Quantum Information & Computation
Quantum Circuit Simplification and Level Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
We perform formal verification of quantum circuits by integrating several techniques specialized to particular classes of circuits. Our verification methodology is based on the new notion of a reversible miter that allows one to leverage existing techniques for simplification of quantum circuits. For reversible circuits which arise as runtime bottlenecks of key quantum algorithms, we develop several verification techniques and empirically compare them. We also extend existing quantum verification tools using SAT-solvers. Experiments with circuits for Shor's number-factoring algorithm, containing thousands of gates, show improvements in efficiency by four orders of magnitude.