Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing
ETS '08 Proceedings of the 2008 13th European Test Symposium
"Split ADC" calibration for all-digital correction of time-interleaved ADC errors
IEEE Transactions on Circuits and Systems II: Express Briefs
A 1.2-V 12-b 120-MS/s SHA-free dual-channel Nyquist ADC based on midcode calibration
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Proceedings of the Conference on Design, Automation and Test in Europe
Analog Integrated Circuits and Signal Processing
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This paper proposes combining the standard histogram method with a stimulus identification algorithm in order to test the integral nonlinearity (INL) of a high-resolution analog-to-digital (AJD) converter without a high-quality sine wave. The major problems in the two techniques are explained in order to appreciate the benefits of the combination. The increased INL estimation accuracy is verified with simulations of 16-b A/D converters under diiTerent conditions, and experimental results of the INL testing of a 16-b AID converter are also quoted to support the theory. The simulations and experimental tests show that the INL of 16-b AID converters can be measured with very simple equipment and that an accurate test stimulus is not necessary.