Convex Optimization
A 2.7ua sub1-v voltage reference
Proceedings of the 21st annual symposium on Integrated circuits and system design
An improved and automated design tool for the optimization of CMOS OTAs using geometric programming
Proceedings of the 21st annual symposium on Integrated circuits and system design
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A CAD methodology to design analog circuits via geometric programming (GP) involving manufacturing issues is proposed. A functional approach by sensitivity analysis from dimensional variables is used to obtain the design space. A mismatch analysis using the Pelgrom's model defines the minimum area to ensure parametric yield requirements. With the information on the design space and minimum area, performance and yield are optimized with a new strategy called best-effort. This methodology is validated through the design of a sub-threshold voltage reference [1]. In this work a 3.25 ppm/C temperature coefficient is obtained with a deviation nine times lower but occupying the same area than the one using the GP strategy without manufacturing issues. Further, it is shown how an appropriate sizing can improve the yield up to 24%.