Communications of the ACM - Special issue on parallelism
Analog VLSI and neural systems
Analog VLSI and neural systems
IEEE Spectrum
Experiments and prospects of Example-Based Machine Translation
ACL '91 Proceedings of the 29th annual meeting on Association for Computational Linguistics
Toward memory-based translation
COLING '90 Proceedings of the 13th conference on Computational linguistics - Volume 3
Massively parallel artificial intelligence
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 1
Massively parallel memory-based parsing
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 2
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In this paper, we describe a design of wafer-scale integration for massively parallel memory-based reasoning (WSI-MBR). WSI-MBR attains about 2 million parallelism on a single 8 inch wafer using the state-of-the-art fabrication technologies. While WSI-MBR is specialized to memory-based reasoning, which is one of the mainstream approachs in massively parallel artificial intelligence research, the level of parallelism attained far surpasses any existing massively parallel hardware. Combination of memory array and analog weight computing circuits enable us to attain super high-density implementation with nanoseconds order inference time. Simulation results indicates that inherent robustness of the memory-based reasoning paradigm overcomes the possible precision degradation and fabrication defects in the wafer-scale integration. Also, the WSI-MBR provides a compact (desk-top size) massively parallel computing environment.