Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
IEEE Transactions on Computers
Template style considerations for sea-of-gates layout generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
An efficient routing algorithm for SOG cell generation on a dense gate-isolated layout style
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Plane parallel a maze router and its application to FPGAs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Steiner trees and CAD algorithms for VLSI systems
Steiner trees and CAD algorithms for VLSI systems
Routing algorithm for gate array macro cells
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A language for describing rectilinear Steiner tree configurations
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Correct and Provably Efficient Methods for Rectilinear Steiner Spanning Tree Generation
Proceedings of the The First Great Lakes Computer Science Conference on Computing in the 90's
A Greedy Heuristic for the Rectilinear Steiner Tree Problem
A Greedy Heuristic for the Rectilinear Steiner Tree Problem
An architecture-independent approach to FPGA routing based on multi-weighted graphs
EURO-DAC '94 Proceedings of the conference on European design automation
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An accurate evaluation of routing density for symmetrical FPGAs
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A router for symmetrical FPGAs based on exact routing density evaluation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
IEEE Transactions on Computers
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