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Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
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ACM Transactions on Computer Systems (TOCS)
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ACM SIGARCH Computer Architecture News
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ACM Transactions on Modeling and Computer Simulation (TOMACS)
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ACM Transactions on Modeling and Computer Simulation (TOMACS)
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ACM SIGARCH Computer Architecture News
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ACM Computing Surveys (CSUR)
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IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
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IEEE Transactions on Computers
The operating system kernel as a secure programmable machine
EW 6 Proceedings of the 6th workshop on ACM SIGOPS European workshop: Matching operating systems to application needs
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Proceedings of the 32nd conference on Winter simulation
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HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
Tradeoffs in the Design of Single Chip Multiprocessors
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Trace-Driven Memory Simulation: A Survey
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Tolerating Late Memory Traps in Dynamically Scheduled Processors
IEEE Transactions on Computers
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Proceedings of the 19th Workshop on Principles of Advanced and Distributed Simulation
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IEEE Transactions on Parallel and Distributed Systems
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)
IEEE Transactions on Computers
Memory behavior of an X11 window system
WTEC'94 Proceedings of the USENIX Winter 1994 Technical Conference on USENIX Winter 1994 Technical Conference
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OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
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Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
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Large-reach memory management unit caches
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Cache isolation for virtualization of mixed general-purpose and real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
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An increasing number of architectures provide virtual memory support through software-managed TLBs. However, software management can impose considerable penalties, which are highly dependent on the operating system's structure and its use of virtual memory. This work explores software-managed TLB design tradeoffs and their interaction with a range of operating systems including monolithic and microkernel designs. Through hardware monitoring and simulations, we explore TLB performance for benchmarks running on a MIPS R2000-based workstation running Ultrix, OSF/1, and three versions of mach 3.0.Results: New operating systems are changing the relative frequency of different types of TLB misses, some of which may not be efficiently handled by current architectures. For the same application binaries, total TLB service time varies by as much as an order of magnitude under different operating systems. Reducing the handling cost for kernel TLB misses reduces total TLB service time up to 40%. For TLBs between 32 and 128 slots, each doubling of the TLB size reduces total TLB service time up to 50%.