An area-efficient multistage 3.0- to 8.5-GHz CMOS UWB LNA using tunable active inductors

Authors:
Md. Mahbub Reja;Kambiz Moez;Igor Filanovsky
Affiliations:
Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Abstract

An area-efficient multistage 3.0- to 8.5-GHz ultra-wideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm2. The measurement results show a power gain S21 of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than -10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V.