VLSI implementation of sub-pixel interpolator for AVS encoder

Authors:
Chen Guanghua;Wang Anqi;Hu Dengji;Ma Shiwei;Zeng Weimin
Affiliations:
School of Mechatronics Engineering and Automation, Shanghai Key Laboratory of Power Station Automation Technology, Shanghai University, Shanghai, P. R. China;School of Mechatronics Engineering and Automation, Shanghai Key Laboratory of Power Station Automation Technology, Shanghai University, Shanghai, P. R. China;School of Mechatronics Engineering and Automation, Shanghai Key Laboratory of Power Station Automation Technology, Shanghai University, Shanghai, P. R. China;School of Mechatronics Engineering and Automation, Shanghai Key Laboratory of Power Station Automation Technology, Shanghai University, Shanghai, P. R. China;Key Laboratory of Advanced Display and System Applications, Ministry of Education & Microelectronic Research and Development Center, Shanghai University, Shanghai, P. R. China
Venue:
LSMS/ICSEE'10 Proceedings of the 2010 international conference on Life system modeling and simulation and intelligent computing, and 2010 international conference on Intelligent computing for sustainable energy and environment: Part II
Year:
2010

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Abstract

Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap filter. In this paper, a high performance VLSI architecture of interpolation supporting AVS Baseline@L4 is presented. Vertical redundant data reuse, horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle. The separated 1-D interpolation filters are used to improve throughput and hardware utilization. The proposed design is implemented on FPGA with operating frequency of 150MHz and can support 1080p (1920×1080)/30fps AVS real-time encoder. It is a useful intellectual property design for real-time high definition video application.