Error-correcting coding theory
Error-correcting coding theory
Digital modulation and coding
Introduction to Trellis-Coded Modulation with Applications
Introduction to Trellis-Coded Modulation with Applications
Parallel high-throughput limited search trellis decoder VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hardware-efficient technique to implement a trellis code modulation decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed low-power viterbi decoder design for TCM decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an efficient architecture for a 4-D eight-phase-shift-keying trellis-coded-modulation (TCM) decoder. First, a low-complexity architecture for the transition metric unit is proposed based on substructure sharing. This scheme significantly reduces the required computation without degrading the performance. Then, a new hybrid T-algorithm for a Viterbi decoder is developed by applying a T-algorithm on both branch metrics (BMs) and path metrics (PMs). TCM encoders usually employ high-rate convolutional codes that yield many more transition paths per state than low-rate codes do. This makes it feasible to purge unnecessary additions by applying the T-algorithm on BMs. Applying the T-algorithm on BMs instead of PMs allows one to move the "search-for-the-optimal" operation out of the add-compare-select-unit (ACSU) loop. Hence, the clock speed will not be affected. In addition, by combining the T-algorithm on BMs and the T-algorithm on PMs, the hybrid T-algorithm can reduce the computations required with the conventional T-algorithm on PMs by as much as 50%.