An area-efficient CMOS bandgap reference utilizing a switched-current technique

Authors:
K. U. Bogoda A. Indika;Shunsuke Okura;Toru Ido;Kenji Taniguchi
Affiliations:
Division of Electrical, Electronic and Information Engineering, Osaka University, Osaka, Japan;Division of Electrical, Electronic and Information Engineering, Osaka University, Osaka, Japan;Division of Electrical, Electronic and Information Engineering, Osaka University, Osaka, Japan;Division of Electrical, Electronic and Information Engineering, Osaka University, Osaka, Japan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Abstract

An area-efficient CMOS bandgap reference (BGR) with switched-current and current-memory techniques is presented. The proposed circuit uses only one parasitic bipolar transistor to generate a reference voltage so that significant area reduction can be achieved. In addition, bipolar transistor device mismatch can be eliminated. The circuit produces an output of about 650 mV, and simulated results show that the temperature coefficient of the output is less than 10.4 ppm/°C in the temperature range from 0 °C to 100 °C. The average current consumption is about 49.5 µA in the above temperature range. Furthermore, the output can be set to almost any value. The circuit was designed and simulated in 0.25-µm CMOS technology. The layout occupies less than 0.0011 mm2 (100 µm × 110 µm).