RF microelectronics
Low Power Digital Frequency Conversion Architectures
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Low-power design of decimation filters for a digital IF receiver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
High-Resolution IF-to-Baseband SigmaDelta ADC for Car Radios
High-Resolution IF-to-Baseband SigmaDelta ADC for Car Radios
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A power-efficient narrow-band tunable digital front end (DFE) for bandpass sigma-delta (ΣΔ) analog-to-digital converters is presented. The proposed architecture introduces a new system topology, splitting the down converter into two mixers and placing a cascaded integrator-comb decimation stage between the two mixers. The first mixer is a quadrature mixer that works at a quarter of the sampling frequency. It is followed by a complex mixer with a tunable frequency. The ΣΔ modulator and the DFE are digitally controlled. The proposed architecture is first analyzed on the system level and then synthesized in a 130-nm CMOS technology. A reduction in the power consumption of about 50% has been achieved by the proposed architecture when compared with the conventional approach.