Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system

Authors:
Hirokazu Morisita;Kenta Inakagata;Yasunori Osana;Naoyuki Fujita;Hideharu Amano
Affiliations:
Keio University, Hiyoshi Yokohama, Japan;Keio University, Hiyoshi Yokohama, Japan;Seikei University, Chofu Tokyo, Japan;ARD Japan Aerospace Exploration Agency, Chofu Yokyo, Japan;Keio University, Hiyoshi Yokohama, Japan
Venue:
ACM SIGARCH Computer Architecture News
Year:
2011

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Abstract

UPACS (Unified Platform for Aerospace Computational Simulation) is one of the practical CFD (Computational Fluid Dynamics) packages supporting various selectability. A custom machine for efficient execution of MUSCL; a core functions of UPACS is implemented on FLOPS-2D (Flexibly Linkable Object for Programmable System); multi-FPGA reconfigurable system. The deep and complicated pipeline structure generated from MUSCL dataflow is divided and optimized into two FPGA boards by using a tuning tool called RER. With optimization of the order of operations and pipeline structure, about 60% utilization of the pipeline is achieved even by using serial links between two boards. The execution time is 6.16-23.19 times faster than that of the software on 2.66 GHz Intel Core 2 Duo processor.