A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator

Authors:
Xiao-Yong He;Kong-Pang Pun;Siu-Kei Tang;Chiu-Sing Choy;Peter Kinget
Affiliations:
The Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong SAR, China;The Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong SAR, China;The Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong SAR, China;The Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong SAR, China;The Department of Electrical Engineering, Columbia University, New York, USA
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2011

Citing 3
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Continuous-time delta-sigma modulators for high-speed A/D conversion: theory, practice and fundamental performance limits
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A 0.5-V wideband amplifier for a 1-MHz CT complex delta-sigma modulator

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A 0.5-V 81.2 dB SNDR audio-band continuous-time Delta-Sigma modulator with SCR feedback

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Abstract

This manuscript reports a 0.5聽V 1-MHz signal bandwidth third-order continuous-time complex ΔΣ modulator for analog-to-digital conversion in GFSK receivers. A special common-mode level arrangement and gate-input self-biased amplifiers allows the modulator to meet the speed requirement at the low supply voltage. Realized in a 0.13-μm triple-well CMOS process and using only standard VT devices, the modulator achieves a peak SNDR of 61.9聽dB, a dynamic range of 65.7聽dB and an image rejection ratio of 46.3聽dB with 3.4-mW consumption at the nominal supply of 0.5聽V, and occupies a die area of 0.9聽mm2.