Continuous-time delta-sigma modulators for high-speed A/D conversion: theory, practice and fundamental performance limits
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator
Analog Integrated Circuits and Signal Processing
A 0.5-V 81.2 dB SNDR audio-band continuous-time Delta-Sigma modulator with SCR feedback
Analog Integrated Circuits and Signal Processing
A 0.5-V 90-dB SNDR 102 dB-SFDR audio-band continuous-time delta---sigma modulator
Analog Integrated Circuits and Signal Processing
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This brief presents a fully differential wideband amplifier for 0.5-V supply. The amplifier employs a gate-input two-stage topology and a dc common-mode feedback circuit with a Miller-amplified capacitor for frequency compensation. Designed in a 130-nm triple-well complementary metal-oxide-semiconductor process with regular VT transistors, the amplifier achieves a simulated performance of 51-dB dc open-loop gain, 112-MHz unity gain bandwidth, and 67° phase margin with a load of 6.5 pF/19.6 kΩ, and consumes 600 µW at 0.5-V supply. The proposed amplifier is incorporated in a continuous-time complex Delta-Sigma modulator with a 1-MHz signal bandwidth and 64 × oversampling ratio. In the simulations, the modulator achieves a 72.5-dB signal-to-noise-plus-distortion ratio and consumes 2.3 mW at 0.5 V.