Low-voltage, high-speed CMOS analog latched voltage comparator using the "flipped voltage follower" as input stage

Authors:
Hugues J. Achigui;Christian Fayomi;Daniel Massicotte;Mounir Boukadoum
Affiliations:
Department of Computer Science, Université du Québec í Montréal, Montréal, Canada and Department of Electrical and Computer Engineering, Université du Québec ...;Department of Computer Science, Université du Québec í Montréal, Montréal, Canada;Department of Electrical and Computer Engineering, Université du Québec í Trois-Rivières, Trois-Rivières, Canada;Department of Computer Science, Université du Québec í Montréal, Montréal, Canada
Venue:
Microelectronics Journal
Year:
2011

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Abstract

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type's analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18@mm CMOS technology, and its measured performance shows 12-bit resolution at 20MHz comparison rate and 1V single supply voltage, with a total power consumption of 63.5@mW.