Design of high performance synchronous digital circuits for evolvable hardware (EHW) application using genetic algorithm

  • Authors:
  • J. Bharathi;P. Sakthivel

  • Affiliations:
  • Department of Electronics and Communication Engineering, Anna University, College of Engineering, Chennai, India;Department of Electronics and Communication Engineering, Anna University, College of Engineering, Chennai, India

  • Venue:
  • EC'05 Proceedings of the 6th WSEAS international conference on Evolutionary computing
  • Year:
  • 2005

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Abstract

This paper presents both the genetic algorithm and the hardware evaluation environment. Results reveal that the genetic algorithm is able to exploit the flexibility provided by novel chromosome architecture, and utilize a combination of primitive gates and macro components from a component library, in order to produce circuits, which operate well within timing restrictions. Evolvable Hardware (EHW) is a new scheme inspired by natural evolution, for designing hardware systems. By exploring a large design search space, EHW may find solutions for a task, unsolvable, or more optimal than those found using traditional design methods. The paper introduces this new approach and outlines how it can be applied for hardware design of the serial bit pattern recognizer. A distinct feature of GA is to directly evolve and evaluate circuits in a HDL within novel environment termed Virtual Chip (VC). The VC evolves circuit structures within a HDL, detailed simulation of each circuit is possible with any technology specific component library. This feature allows accurate analysis of timing and area. The GA is able to exploit the flexibility provided by novel chromosome architecture, and utilizes a combination of primitive gates and macro components from a component library in order to produce circuits, which operates well within timing restrictions.