Stochastic Neural Computation I: Computational Elements
IEEE Transactions on Computers
A novel FPGA architecture supporting wide shallow memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deterministic bit-stream digital neurons
IEEE Transactions on Neural Networks
Implementation issues of neuro-fuzzy hardware: going toward HW/SW codesign
IEEE Transactions on Neural Networks
A new digital pulse-mode neuron with adjustable activation function
IEEE Transactions on Neural Networks
Implementation of a new neurochip using stochastic logic
IEEE Transactions on Neural Networks
A new architecture for digital stochastic pulse-mode neurons based on the voting circuit
IEEE Transactions on Neural Networks
Implementation of Central Pattern Generator in an FPGA-Based Embedded System
ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
| Hi-index | 0.00 |
An area-efficient pulse mode hardware neuron model with sigmoidlike activation function for artificial neural networks implementations is presented. The neuron activation function is based on an enhanced version of the voting circuit previously reported in the literature. The proposed model employs pulse stream computations and statistical saturation to deal with the nonlinearities inherent to neural computations. This approach provides an embedded hardware implementation feasibility favoring silicon area efficiency rather than speed. Implementation results on Field Programmable Gate Array (FPGA) technology shows the proposed neuron model requires fewer hardware resources than previous implementations and it is especially attractive for neurons with wide receptive fields in large neural networks. Experimental results are presented to highlight the improvements of the proposed model.