Field programmable gate arrays and floating point arithmetic

Authors:
Barry Fagin;Cyril Renard
Affiliations:
Department of Computer Science, United States Air Force Academy, CO;IRESTE, University of Nantes, France
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

Citing 2
Cited 1

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Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

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Abstract

We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. FPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual undertow. These costs arc analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.