A multiscale model of adaptation and spatial vision for realistic image display
Proceedings of the 25th annual conference on Computer graphics and interactive techniques
Gradient domain high dynamic range compression
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Fast bilateral filtering for the display of high-dynamic-range images
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Photographic tone reproduction for digital images
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Tone Reproduction for Realistic Images
IEEE Computer Graphics and Applications
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Interactive time-dependent tone mapping using programmable graphics hardware
EGRW '03 Proceedings of the 14th Eurographics workshop on Rendering
Perception-motivated high dynamic range video encoding
ACM SIGGRAPH 2004 Papers
A real-time FPGA-based architecture for a Reinhard-like tone mapping operator
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Analog Integrated Circuits and Signal Processing
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Due to recent advances in high dynamic range (HDR) technologies, the ability to display HDR images or videos on conventional LCD devices has become more and more important. Many tone-mapping algorithms have been proposed to meet this end, the choice of which depends on display characteristics such as luminance range, contrast ratio and gamma correction. An ideal HDR tone-mapping processor should have a robust core functionality, high flexibility, and low area consumption, and therefore an ARM-core-based system-on-chip (SOC) platform with a HDR tone-mapping application-specific integrated circuit (ASIC) is suitable for such applications. In this paper, we present a systematic methodology for the development of a tone-mapping processor of optimized architecture using an ARM SOC platform, and illustrate the use of this novel HDR tone-mapping processor for both photographic and gradient compression. Optimization is achieved through four major steps: common module extraction, computation power enhancement, hardware/software partition, and cost function analysis. Based on the proposed scheme, we present an integrated photographic and gradient tone-mapping processor that can be configured for different applications. This newly-developed processor can process 1,024 脳 768 images at 60 fps, runs at 100 MHz clock and consumes a core area of 8.1 mm2 under TSMC 0.13 μm technology, resulting in a 50% improvement in speed and area as compared with previously-described processors.