Time-interleaved pipeline ADC design: a reconfigurable approach supported by optimization

Authors:
Wilmar Carvajal;Wilhelmus Van Noije
Affiliations:
Integrable Systems Technological Laboratory, São Paulo, Brazil;University of São Paulo, USP, São Paulo, Brazil
Venue:
Proceedings of the 24th symposium on Integrated circuits and systems design
Year:
2011

Citing 1
Cited 1

Multilevel power optimization of pipelined A/D converters

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

An optimization-based reconfigurable design for a 6-bit 11-MHz parallel pipeline ADC with double-sampling S&H

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)

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Abstract

This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced throughout the design in a CMOS 0.35 μm AMS technology. The goal is accomplished by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction and Geometric Programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Pre-layout simulations of different blocks and the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal.