Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An 8-bit 120-MS/s interleaved CMOS pipeline ADC based on MOS parametric amplification
IEEE Transactions on Circuits and Systems II: Express Briefs
Multilevel power optimization of pipelined A/D converters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Time-interleaved pipeline ADC design: a reconfigurable approach supported by optimization
Proceedings of the 24th symposium on Integrated circuits and systems design
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This paper presents a 6 bit, 11MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 µm AMS technology, and some postlayout results are shown.