Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Video processing requirements on SoC infrastructures
Proceedings of the conference on Design, automation and test in Europe
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
Development of a soc for digital television set-top box: architecture and system integration issues
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
| Hi-index | 0.00 |
Embedded consumer electronics like video processing systems require large storage capacity and high bandwidth memory access. Also, those systems are built from heterogeneous processing units, designed specifically to perform dedicated tasks in order to maximize the processing efficiency. A single off-chip memory is shared between the processing units to reduce power and save costs. The external memory access is the system bottleneck when decoding high definition video sequences in real time. A four level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The inclusion of the memory hierarchy in the system has also implications on system integration and IP reuse in a collaborative design. This work presents some issues in the integration of the memory hierarchy on the system and practical strategies used to solve them. This architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.