Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Video processing requirements on SoC infrastructures
Proceedings of the conference on Design, automation and test in Europe
A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Integration issues on the development of an h.264/AVC video decoder SoC for SBTVD set top box
Proceedings of the 24th symposium on Integrated circuits and systems design
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
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This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.