Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
Integration issues on the development of an h.264/AVC video decoder SoC for SBTVD set top box
Proceedings of the 24th symposium on Integrated circuits and systems design
Development of a soc for digital television set-top box: architecture and system integration issues
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
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Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large storage capacity and high bandwidth while data accesses can be irregular. The SoC architectures used for implementing these applications typically contain a heterogeneous collection of processing elements and use a single interface to off-chip DRAM in order to provide the required storage capacity at a low cost. Proper integration of interconnect and memory architecture is required to achieve the required bandwidths and latencies for accessing memory. The application requirements as well as the characteristics and constraints for accessing memory are key inputs for NoC design. Future memory technologies may cause a paradigm shift by offering high-bandwidth memory access, possibly via multiple memory interfaces.